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Key
Technologies
The following technologies are currently under development:
Neo-Stack ™
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Accommodates a variety of dice in the same stack (4-50 layers) and multiple dice per layer
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Bare stack footprint is the same as largest die, plus 25 mils on all sides
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Easily accommodates die shrinks

Bendable Circuits
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Off-shoot of thinning process for Neo- Stacks
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Thickness: < 50 microns
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Bendable, twistable interconnection between flexible circuits and flexible substrates
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Core technology for wearable bio-monitor and conformal electronics

3DANN™
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3D Artificial Neural Network (aka "Silicon Neuron")
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High speed, compact image processing and human-level recognition capabilities
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Core technology for
VIP/Balboa Image Processing Board, the Silicon Brain initiative, and the SuperRouter development.

High Density Interconnects / Photonics Communication
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Optical interconnects and switching are believed to be the key enabling technologies to achieve Terabit per second processing speed in a volume of a few cubic inches
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Irvine Sensors is a Member, University of California at San Diego (UCSD)-led consortium developing a massively parallel, optically switched processor core for computers - a marriage of the electronic densities available with Irvine Sensors' proprietary chip-stacking processes and the speeds which can be realized by optically switching parallel interconnections between such dense structures - expected to permit a breakthrough in processing speed for classes of applications that are presently limited by computer bus architectures. Potential to be a powerful adjunct to 3DANN ™
Core technology for: - Silicon Brain - High speed Data Communications and Telecom Switches - A wide range of applications including servers, portable computer systems, cable TV, and fiber optics-to-the- home

SuperRouter™
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Serial data rates to 160 GHz
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Ultra low reconfiguration latency for ATMs
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Super computing via the Internet
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Unique ISC and TRW technologies
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Product potential as an Internet2 enabler

Silicon Brain
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Unifying principle is to emulate the human central nervous system
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3D Field-Effect Transistor (3D-FET) interconnect technology is a key enabling development
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Expected to eventually attain Petaflop performance, i.e., quadrillions of operations per second
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Anticipated to achieve the same volumetric efficiency as the human brain in one-third of a cubic foot (about the size of a shoebox) and using less than ten watts of power

Article:
"Chip Stack Aims for Brain-like Connectivity"
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